2. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, it relates to a contact electrode structure for such device.
2. Description of the Prior Art
FIG. 1 is a sectional view showing a contact electrode structure of a conventional semiconductor device. As shown in FIG. 1, a p-type layer 2 having a thickness of x is formed on an n-type silicon substrate 1 and an insulating layer 4 is formed on the p-type layer 2. The insulating layer 4 has a contact hole 5 formed in a specified portion thereof so that a surface of the p-type layer 2 is exposed. Further, an aluminum layer 3 of an aluminum alloy is provided on the insulating layer 4 so that the aluminum layer 3 is electrically connected through the contact hole 5 to the p-type layer 2. A potential being more than 5 volt is applied to the n-type silicon substrate 1 as a substrate potential. A potential of 0 to 5 volt is applied to the p-type layer 2 through the aluminum layer 3. Therefore, a reverse bias potential is applied to a p-n junction part between the n-type silicon substrate 1 and the p-type layer 2. Generally, when a power source potential is 5 V, voltage-proof in the junction betWeen the n-type silicon substrate 1 and the p-type layer 2 is required at least 10 V or so.
However, even if the junction part between the n-type silicon substrate 1 and the p-type layer 2 has sufficient voltage-proof, microscopically some leakage current may flow through the junction part. Especially with a dynamic random access memory (DRAM), it is important to reduce the leakage current in view of the performance characteristics required of the memory.
As a factor of increasing the leakage current, it can be pointed out that a pit is produced by a reaction between the p-type layer 2 and the aluminum layer 3. The cause of such pit being produced can be explained by the following fact. The semiconductor device shown in FIG. 1 is subjected to various kinds of heat treatment in a following process. In the stage of heat treatment, a maximum applicable temperature is about 450.degree. C. The solid solubility of silicon in aluminium at this temperature is 0.48 wt %. Therefore, when the semiconductor device is subjected to heat treatment at 450.degree. C., the silicon component of the p-type layer 2 is diffused to aforesaid solid solubility limit into the aluminum alloy which constitutes the aluminum layer 3. In order to prevent such reaction, it is a usual practice to alloy the aluminum layer 3 with silicon in a quantity of more than the solid solubility limit so that the silicon in the aluminum is supersaturated. However, even if such approach is taken, the distribution of a concentration of the silicon in the aluminum layer 3 is not uniform and, therefore, in the aluminum layer 3 there is present a portion in which the concentration of the silicon in the aluminum layer 3 is lower than the solid solubility limit. Thus, such portion in the aluminum layer 3 and the p-type layer 2 will react with each other in the above mentioned manner.
If the silicon component of the p-type layer 2 is diffused in the aluminum layer 3 in such way, a hole is formed in the p-type layer 2 as shown in FIG. 2, and some aluminum from the aluminum layer 3 enters the hole to form a pit 10. When the thickness x of the p-type layer 2 is sufficiently large as compared with the pit 10 so formed, there is no problem of increasing the leakage current.
Recently, however, as the semiconductor device is required higher integration, the thickness x of the p-type layer 2 is becoming smaller. When the thickness x of the p-type layer 2 is so small as to permit a pit 10 to bring into contact with the n-type silicon substrate 1 by growth through the p-type layer 2, the n-type silicon substrate 1 and the aluminum layer 3 are electrically connected to each other by the pit 10, which naturally leads to the problem of increasing the leakage current.
As an approach for solving such problem, it has been proposed to provide such a barrier metal layer as shown in FIG. 4. A device shown in FIG. 4 has three points of difference from the device shown in FIG. 1. First, a barrier metal layer 11 formed of such material as TiW, TiN, or W is provided on a portion of a p-type layer 2 which corresponds to the bottom of a contact hole 5 and on a insulating layer 4, Second, an aluminum layer 3 is formed on the barrier metal layer 11. Further, the p-type layer 2 and the aluminum layer 3 are electrically connected through the barrier metal layer 11 In other respects, the device shown in FIG. 4 is entirely same as the device shown in FIG. 1.
The barrier metal layer 11 effectively acts as a barrier between the p-type layer 2 and the aluminum layer 3 at temperature of up to the order of 400.degree.-500.degree. C., but no such effect can be expected of it at temperature of more 500.degree. C., particularly 550.degree. C. In practice, therefore, such proposed structure shown in FIG. 4 involves same problem as encountered with the earlier mentioned conventional structure.
As another approach, it has been proposed to provide a silicide layer as shown in FIG. 5. A device shown in FIG. 5 has three points of difference from the device shown in FIG. 1. First, a silicide layer 12 is formed on a portion of a p-type layer 2 which corresponds to the bottom of a contact hole 5. Second, an aluminum layer 3 is formed on the silicide layer 12 and an insulating layer 4. Further, the p-type layer 2 and the aluminum layer 3 are electrically connected through the silicide layer 12. In other respects, the device in FIG. 5 is entirely same as the device shown in FIG. 1.
In such a semiconductor device, when ion implantation for forming the silicide layer 12 or ion implantation in any later stage is performed, some of the metallic atoms which constitute the silicide layer 12 will be transferred to a vicinity of a junction part between an n-type silicon substrate 1 and the p-type layer 2. In one method for forming the silicide layer 12, a specified metal layer (not shown) is formed on the p-type layer 2 and subsequently the metallic atom constituting the metal layer is thermally diffused. In this method, during the stage of thermal diffusion, the metallic atoms are diffused to the vicinity of the junction part between the n-type silicon substrate 1 and the p-type layer 2. In another method, ion mixing is carried out after a metal layer is formed on the p-type layer 2, and then the silicide layer 12 is formed by heat treating. In such method, metallic atoms are knocked on by the ion energy applied to a surface of the metal layer during the stage of ion mixing, and thus not only are the metal ions diffused into a top portion of the p-type layer 2, but they are scattered to the vicinity of the junction part between the n-type silicon substrate 1 and the p-type layer 2. In some case, ion implantation is carried out in the manufacturing process after the silicide layer 12 is formed. During this stage of ion implantation, the metallic atoms in the silicide layer 12 are knocked on by the energy of the ions, so that they may be scattered to the vicinity of the junction part between the n-type silicon substrate 1 and the p-type layer 2.
If some of the metallic atoms constituting the silicide layer 12 are transferred to the vicinity of the junction in this way, those metallic atoms will become a recombination center Thus, the recombination center acts as a path for the leakage current to increase the leakage current in the junction.
When such a barrier metal layer 11 or such a silicide layer 12 is formed, stress is exerted to the p-type layer 2. The stress concentrates especially on a region corresponding to the contact hole 5. As a result, there will arise a problem that the junction part between the n-type silicon substrate 1 and the p-type layer 2, which corresponds to the contact hole 5, is deteriorated in its operating characteristics.